1. Field of the Invention
The present invention relates to a semiconductor device for a semiconductor LSI, and more particularly to a lightly doped drain (hereinafter, referred to as LDD) layer structure and a technique of forming the same.
2. Description of the Background Art
An LDD layer structure has been conventionally used in a MOSFET to prevent deterioration in hot carrier. For example, FIG. 10 is a vertical section showing an n-type MOSFET with single LDD layer structure as a first prior art. As shown in FIG. 10, a semiconductor device 1P1 where a gate insulating film 11P and a gate electrode 5P are formed in this order on a surface of a semiconductor substrate 2P having a p-well formed by ion-implantation with boron (B) is once implanted with phosphorus (P) ion or arsenic (As) ion to form LDD layers 8P and 10P almost symmetrically and after that, a sidewall 6P is formed and then arsenic ion or the like is further implanted and diffused to form high-concentration (n+) source/drain regions 3P and 4P. For reference, a flow of manufacturing the n-type MOSFET of FIG. 10 is shown in FIG. 11.
As a second prior art which is a variation of the first prior art, an n-type MOSFET with double LDD layer structure is proposed in Japanese Patent Application Laid Open Gazette No. 7-297393. The structure of this n-type MOSFET 1P2 is shown in FIG. 12. In the n-type MOSFET 1P2 of FIG. 12, an arsenic ion is once implanted to form the inner LDD layers 8P and 10P in the same manner as the first prior art, and outer LDD layers 7P and 9P made of P layer with high diffusion coefficient are formed by utilizing diffusion through a heat treatment, covering the inner LDD layers 8P and 10P, respectively.
(1) The MOSFET with single LDD layer structure of the first prior art has an advantage that the LDD layers (arsenic layers 8P and 10P of FIG. 10) relieve a drain electric field to thereby improve hot-carrier resistance and withstand voltage. On the other hand, the MOSFET with single LDD layer structure has a disadvantage that the LDD layers work as parasitic resistance between the source and drain to thereby deteriorate driving capability.
(2) In the double LDD layer structure of the second prior art, a double-layered structure consisting of the outer P layer of relatively low concentration and the inner arsenic layer of relatively high concentration located near a surface forms a step-like impurity concentration distribution, and therefore the LDD layer made of P of relatively low concentration relieves the drain electric field and the LDD layer made of arsenic of relatively high concentration reduces the resistance element, to thereby achieve a driving capability higher than the first prior art.
This structure of the second prior art, however, causes a new problem that a region where a sum of the concentration distributions of the arsenic layer of relatively high concentration and the phosphorus layer of relatively low concentration varies in a step-like manner is created inside the semiconductor substrate, to locally generate a strong electric field therein, and consequently the hot-carrier resistance is deteriorated as compared with the structure of the first prior art. To clarify this point, an impurity concentration distribution with respect to a horizontal direction in parallel with the surface of the semiconductor substrate (an impurity concentration distribution at the depth of 0.5 xcexcm inside the semiconductor substrate from an interface between the gate insulating film and the surface of the semiconductor substrate) in the n-type MOSFET of double LDD structure as shown in FIG. 12 of Japanese Patent Application Laid Open Gazette No. 7-297393 is simulated by the inventor of the present invention. The simulation result (not known) is shown in FIG. 13.
In FIG. 13, the horizontal axis represents a horizontal direction x of FIG. 12 with the position x=0.001 xcexcm indicating a center portion of the surface of the semiconductor substrate 2P sandwiched by end portions of the phosphorus layers 7P and 9P (nxe2x88x92(2)) of FIG. 12, and the vertical axis y of FIG. 13 represents a vertical direction y from the center portion towards the inside of the semiconductor substrate 2P. As shown in FIG. 13, the concentration of phosphorus which is an impurity element of the outer LDD layer increases from 1E16 cmxe2x88x923 to 1E18 cm3 with relatively great gradient and from the position x=0.08 xcexcm of FIG. 13, the concentration of arsenic sharply increases with a gradient greater than that of phosphorus. Since the inner LDD layers 8P and 10P of FIG. 12 include both impurities, phosphorus and arsenic, the impurity concentration of the inner LDD layers 8P and 10P is the sum of both concentrations of phosphorus and arsenic from the position x=0.08 xcexcm of FIG. 13 (end portions of the LDD layers 8P and 10P) and therefore sharply increases. Especially, at an intersection P1 of FIG. 13, as the concentrations of both impurities, that is, phosphorus and arsenic are equal to each other, the impurity concentration of the LDD layers 8P and 10P of FIG. 12 sharply increases up to almost twice in a step-like manner. Further, since a region P2 of FIG. 13 is a junction between the LDD layer 8P (10P) and n+ layer 3P (4P), the concentration connection becomes a step-like one also in this region.
Thus, it is disadvantageous that the second prior art can show only intermediate characteristics between the single LDD layer structure of the first prior art and a single drain structure in an integrated evaluation of its characteristics such as driving capability, withstand voltage and hot-carrier resistance.
The present invention is directed to a semiconductor device. According to a first aspect of the present invention, the semiconductor device comprises: a semiconductor substrate having a channel impurity of a first conductivity type; a first high-concentration impurity region formed from a first surface region in a surface of the semiconductor substrate towards the inside of the semiconductor substrate, having at least one kind of impurity of a second conductivity type whose concentration is higher than that of the channel impurity; an insulating film formed on a second surface region adjacent to the first surface region in the surface of the semiconductor substrate; a control electrode formed on a surface of the insulating film; a second high-concentration impurity region formed from a third surface region adjacent to the second surface region in the surface of the semiconductor substrate towards the inside of the semiconductor substrate, being opposed to the first high-concentration impurity region, having the at least one kind of impurity identical to that of the first high-concentration impurity region; and a first lightly doped drain layer formed from a fourth surface region in the second surface region on the side of an interface between the first and second surface regions towards the inside of the semiconductor substrate, being joined to at least part of an end surface of the first high-concentration impurity region opposed to the second high-concentration impurity region, having a first impurity of the second conductivity type whose concentration is lower than that of the at least one kind of impurity in the first and second high-concentration impurity regions. In the semiconductor device of the first aspect, the first lightly doped drain layer comprises a first main distribution having a first concentration gradient corresponding to an impurity concentration variation with respect to a horizontal direction in which an end surface of the control electrode is viewed from a center portion of the control electrode in parallel to the surface of the semiconductor substrate, where the first impurity is distributed inside the semiconductor substrate; and a first tail distribution having a second concentration gradient which is smaller than the first concentration gradient and provides a gradual increase in concentration of the first impurity towards the concentration of the channel impurity, where the first impurity is distributed inside the semiconductor substrate deeper than the first main distribution.
According to a second aspect of the present invention, the semiconductor device of the first aspect further comprises: a second lightly doped drain layer formed from a fifth surface region located from the interface between the first and second surface regions up to an inner side of an end of the fourth surface region in the first lightly doped drain layer towards the inside of the first lightly doped drain layer, being joined to the end surface of the first high-concentration impurity region, having a second impurity of the second conductivity type whose concentration is lower than that of the at least one kind of impurity in the first and second high-concentration impurity regions and the first impurity. In the semiconductor device of the second aspect, the second lightly doped drain layer comprises a second main distribution having a concentration distribution with respect to the horizontal direction which can compensate a decrease in the concentration of the first impurity near a junction between the first main distribution and the end surface of the first high-concentration impurity region, where the second impurity is distributed inside the second lightly doped drain layer.
According to a third aspect of the present invention, the semiconductor device of the second aspect further comprises: a first nitrogen layer formed from the fifth surface region towards the inside of the second lightly doped drain layer.
According to a fourth aspect of the present invention, the semiconductor device of the second aspect further comprises: a third lightly doped drain layer formed from a six surface region in the second surface region on the side of an interface between the second and third surface regions towards the inside of the semiconductor substrate, being joined to at least part of an end surface of the second high-concentration impurity region, having a third impurity of the second conductivity type whose concentration is lower than that of the at least one kind of impurity in the first and second high-concentration impurity regions. In the semiconductor device of the fourth aspect, the third lightly doped drain layer comprises a third main distribution having a third concentration gradient, where the third impurity is distributed inside the semiconductor substrate; and a second tail distribution having a fourth concentration gradient which is smaller than the third concentration gradient and provides a gradual increase in concentration of the third impurity towards the concentration of the channel impurity, where the third impurity is distributed inside the semiconductor substrate deeper than the third main distribution.
According to a fifth aspect of the present invention, the semiconductor device of the fourth aspect further comprises: a fourth lightly doped drain layer formed from a seventh surface region located from the interface between the second and third surface regions up to an inner side of an end of the sixth surface region in the third lightly doped drain layer towards the inside of the third lightly doped drain layer, being joined to the end surface of the second high-concentration impurity region, having a fourth impurity of the second conductivity type whose concentration is lower than that of the at least one kind of impurity in the first and second high-concentration impurity regions and the third impurity. In the semiconductor device of the fifth aspect, the fourth lightly doped drain layer comprises a fourth main distribution having a concentration distribution with respect to the horizontal direction which can compensate a decrease in the concentration of the third impurity near a junction between the third main distribution and the end surface of the second high-concentration impurity region, where the fourth impurity is distributed inside the third lightly doped drain layer.
According to a sixth aspect of the present invention, the semiconductor device of the fifth aspect further comprises: a second nitrogen layer formed from the seventh surface region towards the inside of the fourth lightly doped drain layer.
According to a seventh aspect of the present invention, the semiconductor device comprises: a semiconductor substrate having a channel impurity of a first conductivity type; a high-concentration impurity region formed from a region in a surface of the semiconductor substrate towards the inside of the semiconductor substrate, having an impurity of a second conductivity type whose concentration is higher than that of the channel impurity; an insulating film formed on a surface region of the semiconductor substrate near an end surface of the high-concentration impurity region; a control electrode formed on a surface of the insulating film; and a first low-concentration impurity region having a first impurity which has a first distribution obtained by implantation with ion from the side of an end surface of the control electrode towards the inside of the semiconductor substrate below the control electrode at a tilt angle made by a normal direction of the surface of the semiconductor substrate and an ion-implantation direction, which can cause a channeling phenomenon, wherein concentration of the first impurity is lower than an impurity concentration in the high-concentration impurity region.
According to an eighth aspect of the present invention, the semiconductor device of the seventh aspect further comprises: a second low-concentration impurity region having a second impurity which has a second distribution obtained by implantation with ion from a surface of the first low-concentration impurity region to the inside of the first low-concentration impurity region at an angle that can not cause the channeling phenomenon, wherein concentration of the second impurity is lower than the impurity concentration of the high-concentration impurity region and both of the first and second impurities are distributed in the low-concentration impurity region.
According to a ninth aspect of the present invention, the semiconductor device of the eighth aspect further comprises: a nitrogen layer formed from a surface region of the second low-concentration impurity region towards the inside of the second low-concentration impurity region.
The present invention is also directed to a method of manufacturing a semiconductor device. According to a tenth aspect of the present invention, the method comprises the steps of: (a) providing a semiconductor substrate, an insulating film and a control electrode formed on a surface of the semiconductor substrate in this order, and an insulative through film formed on a surface region of the semiconductor substrate in an active region in the vicinity of an end surface of the insulating film, the insulative through an film having a thickness smaller than that of the insulating film; and (b) ion-implanting a first impurity through the insulative through film towards the inside of the semiconductor substrate below the control electrode at a first tilt angle which is an angle made by a normal direction of the surface of the semiconductor substrate and an ion-implantation direction and can cause a channeling phenomenon, to form a first impurity layer where a first impurity is distributed.
According to an eleventh aspect of the present invention, the method of the tenth aspect further comprises the step of: (c) ion-implanting a second impurity through the insulative through film from an surface region of the first impurity layer towards the inside of the first impurity layer at a second tilt angle that can not cause the channeling phenomenon, to form a second impurity layer inside the first impurity layer, where both the first and second impurities are distributed.
According to a twelfth aspect of the present invention, the method of the eleventh aspect further comprises the step of: (d) ion-implanting nitrogen through the insulative through film from a surface region of the second impurity layer towards the inside of the second impurity layer at a third tilt angle that can not cause the channeling phenomenon, to form a nitrogen layer inside the second impurity layer near the surface region.
In the semiconductor device of the first aspect, since the first lightly doped drain layer has the first tail distribution extending up to relatively great depth in (the channel portion of) the semiconductor substrate and the first tail distribution has the concentration gradient which gradually increases up to about the channel impurity concentration with respect to the horizontal direction, the junction between the first impurity providing the first tail distribution of the first lightly doped drain layer and the channel impurity in the semiconductor substrate is a pn junction between low-concentration impurities and the depletion layer created in the pn junction is widened in its range. This remarkably relieves a drain electric field and more significantly improves a withstand voltage and a hot-carrier resistance than in the prior-art MOSFETs with single and double lightly doped drain layers.
In the semiconductor device of the second aspect, the low-concentration distribution created in the region within the first main distribution region of the first lightly doped drain layer and near the junction between the first lightly doped drain layer and the first high-concentration impurity region can be compensated by the concentration of the second impurity of the same conductivity type in the second lightly doped drain layer, and this makes it possible to form an impurity concentration distribution, in the region where the first and second main distributions are overlapped, at a relatively shallow depth from the surface of the semiconductor substrate, where the impurity concentration distribution which is the sum of concentrations of the first and second impurities can be connected smoothly to the impurity concentration in first high-concentration impurity region. As a result, the low-concentration layer created near the surface of the semiconductor substrate by the first lightly doped drain layer, i.e., local generation of high electric field caused by the high-resistance layer can be sufficiently prevented to avoid a fall of on current and a driving capability higher than that of the prior-art MOSFET with single lightly doped drain layer structure is achieved.
In the semiconductor device of the third and sixth aspects, since a dangling bond created in the interface between the semiconductor substrate and the insulating film can be terminated by nitrogen, a further improvement in hot-carrier resistance is achieved through reduction in interface state.
In the semiconductor device of the fourth aspect, since the junction between the third impurity of low concentration which forms the second tail distribution in the third lightly doped drain layer and channel impurity of low concentration is created at a relatively great depth from the surface of the semiconductor substrate to widen the range of the depletion layer, a drain electric field can be further relieved and a hot-carrier resistance can be further improved.
In the semiconductor device of the fifth aspect, since the fourth lightly doped drain layer is superimposed within the low-concentration region which is created by the third lightly doped drain layer at a relatively shallow depth by nature, the above low concentration created by the third impurity is compensated by the concentration of the fourth impurity, to smoothly connect the impurity concentration distribution which is the sum of concentrations of the third and fourth impurities to the impurity concentration within the second high-concentration impurity region. Therefore, generation of the high-resistance layer created by the third lightly doped drain layer at relatively shallow depth from the surface of the semiconductor substrate, i.e., local generation of high electric field can be effectively prevented, to achieve a still higher driving capability.
In the semiconductor device of the seventh aspect, the electric field is sufficiently relieved by using the tail distribution of the first impurity through the channeling phenomenon, to improve a hot-carrier resistance.
In the semiconductor device of the eighth aspect, the impurity concentration created near the surface region by the first low-concentration impurity region can be compensated by the second impurity concentration, and deterioration in driving capability caused by the sufficient improvement in hot-carrier resistance is sufficiently prevented, to improve the driving capability.
In the semiconductor device of the ninth aspect, a further improvement in hot-carrier resistance is achieved.
In the method of the tenth aspect, only by using the ion implantation step where the first impurity is ion-implanted at the first tilt angle with which the channeling phenomenon can be caused, a remarkable improvement in hot-carrier resistance is ensured with easy and reliable process.
In the method of the eleventh aspect, only by addition of one ion implantation step where the second impurity is further ion-implanted at the second tilt angle, an improvement in driving capability is also achieved.
In the method of the twelfth aspect, since the nitrogen implantation is performed after forming a sufficient channeling tail distribution up to the great depth from the surface of the semiconductor substrate, the dangling bond near the surface of the semiconductor substrate can be terminated reliably by the implanted nitrogen.
An object of the present invention is to achieve a driving capability higher than that of the first prior art by preventing deterioration in driving capability while improving a hot-carrier resistance by relieving a drain electric field more than in the first and second prior arts.